Engineers have approached the problem of processing digital signals at high frequencies over the last three decades. Typically the industry has been working with two types of transistor processes to deal with digital logic functions: bi-polar and Complementary Metal Oxide Semiconductors (CMOS). The bipolar process provides higher processing speeds due to the inherent ability of bipolar circuits to operate faster. However, typical bipolar designs have high power usage and a low level of integration. CMOS transistor processes have the advantage of very high levels of integration and relatively low power consumption as compared to their bi-polar cousins.
Since the CMOS process is typically slower than bi-polar, engineers must innovate in order to increase operating frequencies of logic in the technology. This has lead to many different approaches to logic families using CMOS process technology. Many different methods exist for implementing high-speed logic. Conventional logic families include conventional CMOS, current-mode logic (CML), and current mode logic with inductive broadbanding. These circuits are designed using deep sub-micron technologies.
These technologies need to be viewed with a comparison of different parameters. For high-speed data processing there are a number of important parameters: speed, power, and area. The most important of the parameters is typically operating frequency or speed. The speed of a logic family is determined by its propagation delay, the time it takes for a logic state to pass from the input to the output. Speed and operating frequency will be used interchangeably herein. The power of the circuit is the amount of current drawn multiplied by the power supply. The area of a circuit is the amount of silicon that the circuit consumes to perform a given operation. Power and area should typically be reduced as much as possible in order to have the highest levels of integration on a device.
Representative examples of conventional logic families will now be described. In particular, conventional CMOS logic families, CML logic families, and CML with inductive broadbanding families will be described. These specific implementations are discussed with respect to the parameters described earlier.
Conventional CMOS
The conventional low power high-density logic family used in the industry today is conventional CMOS logic. This logic family uses rail-to-rail logic that has virtually no static current and thus draws relatively little power. It consumes only a small amount of area. However, it has the drawback that it is relatively slow from what is required in the industry today. For the rest of this patent disclosure “conventional CMOS logic” and “CMOS logic” will both be used interchangeably.
A CMOS logic gate uses both PMOS and NMOS transistors. FIG. 1 shows a typical NAND gate. The PMOS transistors are used to evaluate a “1” state and the NMOS transistors are used to evaluate a “0” state.
The issue with this method of logical function is that the PMOS devices generally need to be sized large than the NMOS transistors because of the fact that the mobility in PMOS (μp) is significantly lower than in the NMOS (μn). The capacitance of a CMOS gate is large and the larger devices cause additional loading. The best performance can be achieved with a PMOS to NMOS width ratio defined by Equation 1. See also, J. M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, N.J.: Prentice-Hall, 1996.
                                          W            p                                W            n                          =                                            μ              n                                      μ              p                                                          Equation        ⁢                                  ⁢        1            
CMOS logic, however, has superior noise immunity. This allows CMOS circuits to operate with lower voltages and with smaller transistor sizes without significant degradation in performance. See also M. Anis, M. Allam, M. Elmasry, “Impact of Technology Scaling on CMOS Logic Styles,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 49, pp. 577-587, August 2002. CMOS logic has high noise margin due to a static path that restores correct logic state in the presence of noise. The noise margin can also be attributed to its large output voltage swing since a logic “1” is identified with a voltage output equal to the supply rail (VDD) and a logic “0” is identified with an output voltage equal to ground (VSS). This large swing means it requires large amounts of voltage noise to switch logic states.
Overall, CMOS logic is the technology standard for high-density processing of digital logic. However, it has severe speed limitations that prevent its usage in many high-speed applications. Engineers have attempted on improving CMOS logic by innovation. Some of these techniques are discussed further.
Current-Mode Logic
One method in which engineers have attempted to improve the performance of logic functions in CMOS is to use a logic family originally called “MOS Current-Mode Logic” (MCML). See, for example, M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, pp. 1181-1187, October 1992; and U.S. Pat. No. 6,424,194 to Hairapetian. MCML is an improvement over CMOS since it uses only of NMOS transistors, which are inherently faster than PMOS transistors. The industry has developed many names for this technology and variations of it, such as the term “SCL.” See, for example, S. Kiaei, S. Chee, D. Allstot, “CMOS Source-Coupled Logic for Mixed-Mode VLSI,” IEEE International Symposium on Circuits and Systems (23rd: 1990: New Orleans) pgs. 1608-1611; and J. Kundan, and S. Hasan, “Enhanced Folded Source-Coupled Logic Technique for Low-Voltage Mixed-Signal Integrated Circuits,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, pp. 810-817, August 2000. The term “C3MOS” has also been used to refer to current-mode logic and variations on the same principles. See, for example, U.S. Pat. No. 6,424,194 to Hairapetian and U.S. Pat. No. 6,340,899 to Green. This type of logic will be referred to herein as “CML.”
A rudimentary CML logic cell is the CML buffer. The CML buffer is shown in FIG. 2. It uses two NMOS input transistors (MP and MN), two output load resistors (RP and RN), and a tail current source of current value (Itail). The inputs are labeled as IP and IN. The outputs are denoted with labels OP and ON.
Current-Mode Logic operates on switching the current (Itail) with the differential pair (MP and MN) between the output resistive loads (RP and RN). When the input voltage difference, IP-IN, is a positive potential more current is steered towards the resister RN than towards the resistor RP. This effectively drops the voltage on the output ON and raises the voltage on output OP, which results in a positive difference on the output nodes (OP-ON). A positive difference indicates a logic “1.” Similarly, when the input voltage difference, IP-IN, is negative more current is steered towards the resistor RP than towards RN. This lowers the voltage on output OP while increasing the voltage on output ON, which results in a negative difference on the output nodes (OP-ON). A negative difference indicates a logic “0.”
Logic functions of an “AND” and an “OR” can also be implemented. The implementation of an AND is shown in FIG. 3. The AND logic function is implemented in current mode logic with two differential NMOS transistor pairs, an NMOS tail current sources with current value (Itail), and resistor loads (RP and RN).
Storage elements may also be created using these elements. A latch can also be created using these elements and is shown in FIG. 4. See also, M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, pp. 1181-1187, October 1992.
The resistance (RP and RN) and the parasitic capacitance determine the speed of the CML cell. The frequency limitation is approximately inversely proportional to the resistance multiplied by the parasitic capacitance. The resistance is determined by the desired output swing (the maximum OP-ON) divided by the desired tail current (Itail). The parasitic capacitance of the output is a combination of parasitic wiring capacitance, capacitance of the drains of the differential pair devices, capacitance of the resistive load and capacitance of the gates of differential pairs in subsequent stages of logic.
The gain of a CML cell is generally defined as (OP-ON)/(IP-IN). The small signal gain of the CML buffer is determined by multiplying the small signal gain (gm) of the differential pair (MP and MN) by the resistor load (RP and RN). The gain of the cell is important since, in order to retain signal strength and increase immunity to noise sources, the gain of the cells must be greater than 1. This remains true over all process, voltage and temperature variations apparent in the circuit.
A significant variation in gain can occur because of the independent variation of gm and resistance over process, voltage and temperature. This extreme variation can lead to difficulties in optimizing of the circuit parameters. This is a significant issue, since the output parasitic capacitance, which directly effects the speed of the cells, has a large dependence on the size of the differential pair (MP/MN). The smaller the differential pair, for a given tail current (Itail) and load resistor (RP/RN), the smaller the gain. Advantageously, the large gain variation limits the minimum transistor size of the differential pair.
The important features of CML are its differential nature and its overall speed. Differential inputs and outputs means that it can have a higher tolerance to noise since the logic state is determined by the difference in voltage potentials and not the absolute voltage potential. CML logic uses only NMOS transistors that are much faster than PMOS transistors. This is because the mobility in NMOS transistors is higher than in PMOS transistors and it accordingly takes a much smaller device to provide the same switching performance than would a PMOS transistor.
Although the operating speeds are much faster than conventional CMOS logic, current-mode logic is still limited in operating frequencies. The speed limitation comes from the parasitic capacitance on the output and the resistor load. Further speed enhancements are required in order to design leading edge high-speed logic.
In summary, current-mode logic provides a reliable method to improve the overall speed performance from the existing CMOS logic. Logic functions and flip-flops using CML are fairly fast and have a reasonably high noise immunity due to its differential nature. However, these cells have significant gain variation over process, voltage and temperature and do not have a bandwidth high enough to handle many of the high-speed applications in leading edge designs.
Current-Mode Logic with Inductive Broadbanding
In order to extend the bandwidth of the CML logic cells, inductive broadbanding techniques can be employed. See, for example, U.S. Pat. No. 6,424,194 to Hairapetian. Using this method, an inductor is placed in series with the resistor. The inductor provides a high frequency boost in order to allow for operation at data rates significantly higher than with regular CML. This technique extends the bandwidth of the CML cells to levels far beyond what is attainable with a purely resistive load.
This technique, illustrated in FIG. 5, increases the overall bandwidth and edge rates of a CML buffer by adding a spiral inductor in series with the resistive output element. This spiral inductor resists the change in current and increases the effective impedance at the output for higher frequencies. This effectively offsets some of the capacitive loading effects and increases overall bandwidth.
The output impedance of the buffer can be analyzed using conventional Laplace-transform analysis techniques. FIG. 6 shows the equivalent model of a single ended buffer load with inductive broadbanding and without inductive broadbanding. Where R represents the resistive element in the respective techniques and L represents the inductive elements in the inductive broadbanding technique. The capacitance on the output CP represents the combined parasitic elements of the output of the buffer.
The output impedance Zin 602 of a purely resistive CML buffer without inductive broadbanding 600 can be summarized in the Laplace frequency domain by Equation 2. See, for example, 22. Ronald E. Thomas and Albert J. Rosa, The Analysis and Design of Linear Circuits, Chapter 10. Englewood Cliffs, New Jersey: Prentice Hall, 1994.
                              Z          in                =                  R                      1            +                                          RC                P                            ⁢              s                                                          Equation        ⁢                                  ⁢        2            
A CML buffer with inductive broadbanding 610 has an output impedance Zin 612 that can be summarized with Equation 3.
                              Z          in                =                              R            +            Ls                                              LCs              2                        +            RCs            +            1                                              Equation        ⁢                                  ⁢        3            
The output impedance of the CML buffer with inductive broadbanding 610 with various inductor values is compared to the purely resistive CML buffer without inductive broadbanding 600 in FIG. 7. The plot shows the obvious improvement in the output impedance of the CML buffer with inductive broadbanding 610 at high frequencies as compared to the purely resistive CML buffer without inductive broadbanding 600. The impedance of the output stage remains larger for higher frequencies than occurs without any inductive broadbanding.
A relatively good magnitude of the inductor used for the inductive broadbanding is linearly proportional to the resistance. See, for example, 10. U.S. Pat. No. 6,340,899 to Green. The output swing (OP-ON) of the CML buffer with inductive broadbanding 610 is equal to the tail current multiplied by the resistance of the load. The desired output swing in many applications is limited by noise tolerance of the system so that for the purposes of circuit optimizations, the swing should remain constant when changing the tail current source. Since the output swing is relatively constant and the inductance magnitude is proportional to the resistance, the magnitude of the inductor is typically scaled inversely with the tail current. For this reason, smaller tail currents typically result in a larger value for the inductors.
Spiral inductors used in implementations of the passive inductor loads consume a relatively large area on silicon. Since the area of the inductor eventually becomes severely restrictive, this places limitations on the smallest possible tail current applicable for the CML buffer with inductive broadbanding 610. Larger tail currents lead to larger power consumption of the CML.
The DC gain of the CML buffer with inductive broadbanding 610 is the same as that of the purely resistive CML buffer without inductive broadbanding 600. The gain is equal to the small signal gain of the differential pair (gm) multiplied by the resistance. This leads to the same type of gain variation as can be seen with the purely resistive CML buffer without inductive broadbanding 600. The similar gain variation leads to the same type of gain related issues as seen with the purely resistive CML buffer without inductive broadbanding 600. For example, the gain variation can render it relatively difficult to select a circuit device size for relatively high operating speeds.
Overall, the CML buffer with inductive broadbanding 610 has a further speed improvement over a purely resistive CML structure that allows for its use in high-speed applications. However, the CML buffer with inductive broadbanding 610 consumes relatively large amounts of area and power and is limited by the same gain variation issues that are seen with the purely resistive CML buffer without inductive broadbanding 600.
Other References
In addition, high-speed differential logic structures are described in the following publications, the disclosures of which are hereby incorporated herein by reference in their entirety: M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans. Electron., vol. E75-C, pp. 1181-1187, October 1992; M. Allam, and M. Elmasry, “Dynamic Current Mode Logic (DyCML): A New Low Power High-Performance Logic Style”, IEEE J. Solid-State Circuits, Vol. 36, pp. 550-558, March 2001; S. Hara, T. Tokumitsu, T. Tanaka, and M. Aikawa, “Broadband monolithic microwave active inductor and its application to miniaturized wide-band amplifiers,” IEEE Trans. Microwave Theory Tech., vol. MTT-36, pp. 1920-1924, December 1998; Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, and F. Masuoka, “0.18 um CMOS 10-Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation,” IEEE J. Solid-State Circuits, Vol. 36, pp. 988-996, June 2001; Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M.Okihara, H. Sakurab, “A 10-Gb/s Demultiplexer IC in 0.18 um CMOS using Current Mode Logic with Tolerance to the Threshold Voltage Fluctuation,” IEEE International Solid-State Circuits Conference (47th: 2000: San Francisco) pgs. 62-63; S. Kiaei, S. Chee, D. Allstot, “CMOS Source-Coupled Logic for Mixed-Mode VLSI,” IEEE International Symposium on Circuits and Systems (23rd: 1990: New Orleans) pgs. 1608-1611; J. Kundan, and S. Hasan, “Enhanced Folded Source-Coupled Logic Technique for Low-Voltage Mixed-Signal Integrated Circuits,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, pp. 810-817, August 2000; U.S. Pat. No. 6,424,194 to Hairapetian; U.S. Pat. No. 6,340,899 to Green; U.S. Pat. No. 6,028,454 to Elmasry, et al.; U.S. Pat. No. 6,320,422 to Koh; U.S. Pat. No. 5,892,382 to Ueda, et al.; U.S. Pat. No. 5,216,295 to Hoang; U.S. Pat. No. 5,945,858 to Sato; U.S. Pat. No. 5,877,642 to Takahashi; U.S. Pat. No. 6,501,314 to Ling; U.S. Pat. No. 4,333,020 to Maerder; U.S. Pat. No. 6,014,041 to Somasekhar, et al.; U.S. Pat. No. 5,726,613 to Hayashi, et al.; and U.S. Pat. No. 5,202,655 to Hara.
Problem Statement
High-speed circuit design in CMOS for leading edge applications has strict requirements for speed, power, and area. Speed is typically required in order for circuits to operate at high data rates and process, transmit, and receive large amounts of data quickly. This speed ideally comes at a minimum cost in power consumption since thermal requirements make high power circuits less cost effective. Minimized area is also desirable to get the highest level of integration possible.
The current state of the art in this area includes conventional CMOS, CML and CML with inductive broadbanding. Conventional CMOS logic has excellent area and power performance, but is limited in its operating speed. The limitation in operating speed is severe enough that it ordinarily can not process data at rates required for leading edge applications. CML circuits have improved speed performance over conventional CMOS logic but are not fast enough for many of the most leading edge applications. CML with inductive broadbanding further increases the speed of resistive CML but consumes an unreasonably large amount of area and power.
A logic family desirably achieves relatively high operating speeds while maintaining relatively low power consumption and relatively small chip area. The current state of the art for high-speed logic circuits using a CMOS process technology has severe limitations for use in low power high frequency applications. Conventional CMOS logic provides a power and area benefit but is severely limited with speed. CML provides some improvements on speed over conventional CMOS, however, does not have the speed required for many leading edge applications and has large gain variations that lead to poorly optimized circuits. CML with inductive broadbanding further improves speed and performance, however, consumes large amounts of area and power, and has the same gain variation issues as purely resistive CML.